Virtual Testertm
Test Program Validation

Reduce Customer Returns, Debug Time
and Test Expenses Using a Virtual ATE

Virtual Testertm
Test Program Validation

Reduce Customer Returns, Debug Time
and Test Expenses Using a Virtual ATE

An ATE-Like Software Tool That
Bridges Design and Test

An ATE-Like Software Tool That Bridges Design and Test

Reduce Customer Returns and Slash Debug Time by up to 90%

No one likes customer returns, nor frustrating debug in production. That’s why we created Virtual Tester (VT).

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The Open Loop Syndrome

Design and test are a world apart, each with their own tools and technical languages. Therefore, going only one way from design to test without validation feedback puts you at risk of having your customers closing this open loop. It also makes it harder and more time-consuming to debug failures reported by Automatic Test Equipment (ATE), directly impacting time-to-market.

Why Wait for Silicon to Find Out?

By bridging design and test, VT can validate your test program long before first silicon. This can greatly decrease customer returns and nasty post-silicon surprises. It can also reduce time-to-market, allowing you to ship much earlier.

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Breakthrough Closed-Loop Technology

Get Faster to Market Using Pre-Silicon Test Program Validation

Closed-loop systems are well-known for their stability, which is why we applied this concept to test engineering. To close the loop, the typical Design-to-Test process is complemented by creating an ATE-aware test bench in the design environment. This allows earlier failure detection, accelerating test program bring up and debug while improving quality.

How VT Works?

Validate Your Test Program Before First Silicon Using a Virtual ATE

VT converts your test program files into an ATE-aware Verilog model that emulates how Automatic Test Equipment drives the DUT. This allows early pre-silicon testing on EDA tools with the same results as post-silicon ATE would produce. It ensures that tests are ATE-compatible, identifies pattern conversion issues, and allows focusing only on Silicon upon ATE failures, making production test debug shorter and more predictable.

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What if There's No Access to the Design?

Conquering Test Program Debug When Design and Test Are on Different Sites

When the test team can’t access the design, using VT can be a challenge as its ATE-aware test bench needs to be simulated with the IC model. Luckily, VT can still be used in such cases, as design and test teams can share the ATE-aware Verilog test bench without sharing the IC model.

Why Test Program Validation by EDA Is Not Enough

EDA tools provide convenient abstractions for designers and as such, they might overlook some production-related considerations. Specifically, EDA environments often ignore ATE hardware limitations and are also unaware of pattern conversion to ATE format. These blindspots can be easily handled when using VT.

Key Features and Benefits

Reduce Customer Returns, Debug Time and Test Expenses

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Early Test Program Validation Using a Virtual ATE

Test Program Debug When Design and Test Are on Different Sites

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