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TDL Design2Test Conversion

Tester Data Link (VCD2STIL + ATEGen) : 

Combine powerful, sophisticated tools with ease of use
Full GUI support

Proven fastest conversion tool in the market
Cleans e/VCD waveforms before timing extraction and cyclization

Handling data with multiple clocks
Aligns edges as specified by user

Clock based sampling and cyclization
Conditional value assignment of signal values based  on other signals

VT Virtual Test

Pre-Silicon Debug

VT simulates the ATE <-> DUT interaction using a simulation test bench created directly from the ATE Test program

 The VT test bench compares DUT respond to ATE vector data and high lights mismatches

Revealing Design/Test issues before first Si and shortening test program debug cycle and time to production


The tool internally translates any format to an event stream. It then compares the two tests and highlights any differences.

The actual signal behavior is compared and identified.

The view shows the differences in the waver, but allows any diff to be tracked down to the source syntax. Thus the user can see the cause and location of each test data difference.

The user can customize the tool activity and make it only compare certain sections or certain signals