Key benefits
• Shorter time to market with the fastest conversion tool and with greater ATE efficiency
• Up to 200X acceleration performing only a single pass even for multiple clock domains
• Shorter debug and higher yield with an ATE-aware test bench validated prior to tapeout
• Superior cyclization thanks to a unique method of clock-based matching
• Faster debug and intuitive environment with a fully-featured GUI
Key features – ATEGen
• Supports IEEE 1450.0, 1450.1, and 1450.2 STIL standard and extensions
• Supports spec-based timing, DC levels, and channel allocation
• Supports very large files (> 24GB)
Key features – VCD2STIL
• Offers three cyclization methods: brute force (sampling), waveform matching (analysis), and clock-based matching
• Cleans e/VCD waveforms before timing extraction and cyclization, removes glitches, aligns user-specified edges, and allows conditional assignment of signal values