Semiconductor test engineers face two main challenges when performing a definitive final test. They must verify that no information is lost during the conversion between the design and testing phases, and produce a final test that is fully aligned with the design goals. Partial or inaccurate test results present a serious quality risk, resulting in device failure, decreased yield, or defective device approval. A closed loop between the design stage and the test environment is essential for final test integrity.
Test Insight’s Tester Data Link (TDL) customizes test patterns that were created using the EDA simulation environment in order to match the unique characteristics of the ATE. Comprising three primary modules - VCD2STIL, ATEGen and VT - the solution creates a definitive link between the design and test phases, increasing productivity and reducing costs. TDL enables advanced program debugging - even before the silicon arrives.
Critical link for a definitive test
TDL provides a high-performance conversion from cycle-based WGL/STIL to tester formats. The solution also supports event-driven formats such as VCD/eVCD to STIL and from STIL to tester. Innovation for accurate conversions - Test Insight raises the level of testing to meet that of the design, resulting in a highly accurate and efficient process and outcome. Enhanced features and direct-to-binary pattern creation save valuable time and reduce the risk of costly errors.
TDL has successfully delivered a tenfold performance increase over alternative solutions.
Commitment to excellence
A trusted partner of major ATE vendors and semiconductor companies, TDL is backed by Test Insight’s renowned customer support.
VCD2STIL - Converts event-driven simulation into cycle-based STIL format patterns
ATEGen - Converts cycle-based test patterns in WGL/STIL formats into target tester program files
VT (Virtual tester) - Interprets the formatted files and creates a test bench simulation that emulates the tester activity inside the design environment