Emulate test patterns in simulation environment with DUT simulation model. The simulation allows pre-silicon debug of test patterns. Reads the intermediate STIL format of tester patterns and creates a Verilog /VHDL simulation test bench. (A sub-set of Virtual tester solution)
During simulation a vcd trace of all device signals and Monitor signals is created. Test cycles indicated in simulation dump Compare window as indicated in VCD trace. DUT response is compared to tester expect data.