Emulate actual tester behavior
Emulate tester patterns in simulation environment with DUT simulation model. The simulation allows pre-silicon debug of test programs. Reads the actual ATE program and creates a Verilog /VHDL simulation test bench.
- Read tester files and create a simulation test bench
- Elegant straight forward solution
- Works with any Verilog / VHDL simulator
- Allows customization
- Leverage existing design environment
- DUT response is compared to tester expect data.
- During simulation a vcd trace of all device signals and monitor signals is created.
- Tester cycles indicated in simulation dump
- Compare window is indicated in VCD trace