Introduction
 Flow
 Features
 Specific Advantages
 Customer Feedbacks


 Supports the following
 system platforms:

 Sun Solaris
    (2.6 and higher)
 Windows NT
    2000 Pro
    XP Pro
 Linux
    (kernel 2.4 and higher)



 Supports variety of
 testers as:


 Verigy V83000
 Verigy V83000f660
 Verigy V93000
 Verigy V93000 Pin Scale
 Teradyne Catalyst
 Teradyne Flex
 Teradyne J750
 Teradyne J971
 Teradyne J973
 Teradyne UltraFLEX
 Advantest T2000
 Advantest T66XX
 Credence Kalos
 Credence Quartet
 Credence STS6120
 Generic STIL
 as standard output
 Generic WGL
 as standard output
 IMS Vanguard
 Inovys Ocelot
 KVD M2
 LTX Fusion CX
 LTX Fusion HF
 LTX SynchroMaster
 LTX Trillium
 MOSAID MS4000
 NPTest Sapphire
 OPENSTAR T2000
 Schlumberger S9K
Overview
 is an innovative pattern conversion program that provides test engineers with an automatic tool for generating Automated Test Equipment (ATE) programs from the designer's simulation data.
Introduction
 generates a test program according to device spec. It avoids the inherent problems that exist when trying to force an event-driven simulation into a constrained ATE test program, by considering device perspective.
 improves communication among project participations. The clear communication is based on common engineering tools, such as timing diagrams, logic-analyzer type wave, and tabular datasheet terms.
The inputs to  are the drawn timing diagrams, the Verilog VCD dump file, EVCD, STIL and WGL. The output is the test program files to run the tester.
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Flow
The diagram below shows the flow of the test program development starting with the device spec, through pattern development, simulation, test program generation and debug using the DUT simulation model.
The wizard platform click to enlarge
Let's look at the different steps:

I. The project is started when the device spec is defined. At this stage, the device designers draw timing diagrams that describe it's operation.
II. Designers typically develop patterns to simulate the device, and verify that the design indeed does what it is intended to. Here starts the main problem of preparing the test program: The simulators used in the design stage are event-driven, and do not behave like the cycle-driven Testers that will test the silicon. This difference is one of the key issues that  is set to solve.
Traditionally, tools that translate event-driven simulation patterns into cycle-based test programs take tester cycles and try to "find" them in the simulation results. This approach is inherently error-prone because it generates "false" and/or "garbage" cycles, that do not fit to the device specification.
 uses a different approach - If you give the software a knowledge of the device spec a-priory, by drawing the device timing diagrams, the translation process into a test program will be much more accurate, and will not contain errors in identifying the correct cycles.
The second problem of using simulation is that it reflects one time point for each event, whereas, in actual silicon the time is a range between the best case and worst-case extremes. Providing the    with the device timing diagrams, that contain the ambiguity regions of the signals timing, solves this problem.    identifies the device cycle that the simulator executes, and then tests it according to the device cycle spec, as it appears in the datasheet. Thereby Wave Wizard generates a test bases on the actual device spec.
Test definition using device specification click to enlarge
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Features
The ease of use of the graphical interface can facilitate the communication between design and test engineers, as they are both looking into device timing diagrams, and not things specific to a paradigm of work. The designers can draw the device spec in   , and use these drawings to publish/print the device spec. They can also verify if their simulation reflects actual device spec - or whether the simulator went astray on the way.
However, it is not necessary that designers be involved in the process, and the test engineers can easily, should they want to, do everything themselves, by replicating device datasheet timing diagrams and executing    against simulation results. The test engineers add tester cycles knowledge either over designer's timing-diagrams or along with the drawing of the diagrams from scratch.
 is a very versatile program, on which the work can be easily split between different people or even between different geographical locations. It can save a great deal of time and effort for the engineer, or alternatively the engineer can use the fine-tuning features to utilize the experience.
The bottom line is the automatic generation of a test program that is proven to require the least amount of debug on the tester, and the least amount of modifications as the product develops in future versions.
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Specific advantages of WaveWizard include
  • Provides early testability validation of the IC design
  • Reduces IC test development time
  • Generates quality test programs
  • Increases productivity, shortens test preparation time,
        and reduces time-to-volume
  • Increases tester utilization for new devices
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Customer Feedbacks
  • "Patterns were generated with less errors"

  • "I originally anticipated that this would take about 2 weeks redesign and complete match with the changes. Using Wave Wizard, we were ready to rerun the patterns in only two hours"

  • "The resulting test program appears to improve the preliminary debug time significantly"
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Event driven to Tester Simulation results -
WGL/STIL ATPG to Tester -
Verification of test program before silicon -
Simulate a test program -
Simulation Data processing -
VCD/EVCD files to tester files -
 new
Directly extract timing into WaveWizard Constructs -
Suite of tools enables users to expand use of STIL - new