Benefit Highlights  Features Highlight  Virtual Wizard  Features: Interactive Online     Pattern Debugger Intuitive Test     engineer's tools set PC Platform -     Windows style GUI Common Wizard     graphical database  Supports the following  system platforms:  Sun Solaris     (2.6 and higher)  Windows NT     2000 Pro     XP Pro  Linux     (kernel 2.4 and higher)	Overview The Virtual Test Wizard  software tool provides several benefits which are not normally available with in house tools. VTW provides a comprehensive solution to one of the most critical challenges in semiconductor test . shortening the time to fully tested parts. Furthermore, it can help you improve yield and reduce the risk of a silicon re-spin. Virtual Test Wizard is a software-based test debug environment. Test development engineers use it to debug and verify ATE test programs against the device simulation model. VTW methodology shortens the time to tested parts by allowing the engineer to develop and debug the ATE program on a workstation, before the silicon is available. Traditionally the critical part of the test development process . the debugging of the program . has to wait for the silicon to become available and access to the tester hardware. With Virtual Test Wizard this changes . test development engineers use VTW to start their program debug early in the product development cycle, well ahead of silicon. VTW methodology brings together the DUT simulation model with a model of the tester that allows engineers to verify and debug their programs right at their desk. Equally important, is using VTW to find problems that would otherwise cause re-spins or yield issues. Modeling the ATE and the DUT together in software allows developers to detect certain problems early on in the product development cycle. A further advantage is the rapid debug made possible by the extra visibility into the DUT internal registers provided by the simulation model. Back to top The wizard platform click to enlarge Benefit Highlights Saves costly re-spins, by detecting problems before tape-out Detects yield issues, when they can be fixed easily Reduces time to tested parts Significantly improves the quality of the test program used on the initial parts and greatly reduces the time required on the ATE to debug test programs Easily complements your existing test development methodologies Used with any Verilog/VHDL simulator Back to top Features Highlight Works with ATE program (independent of method used to generate program) Uses the same device model used/developed by the designer. No need for any extra work or modification Checks for DUT and tester contention Indication in the simulation trace of tester cycle, Timeset, strobe position User customization of tester files is possible Simulation can be done in user design environment. The test engineer can run the virtual test and send the test bench files to the design team for simulation Back to top	Event driven to Tester Simulation results - WGL/STIL ATPG to Tester - Verification of test program before silicon - Simulate a test program - Simulation Data processing - VCD/EVCD files to tester files -  new Directly extract timing into WaveWizard Constructs - Suite of tools enables users to expand use of STIL - new