Supports the following
 system platforms:

 Sun Solaris
    (2.6 and higher)
 Windows NT
    2000 Pro
    XP Pro
 Linux
    (kernel 2.4 and higher)




 Verigy V83000
 Verigy V83000f660
 Verigy V93000
 Verigy V93000 Pin Scale
 Teradyne Catalyst
 Teradyne Flex
 Teradyne J750
 Teradyne J971
 Teradyne J973
 Teradyne UltraFLEX
 Advantest T2000
 Advantest T66XX
 Credence Kalos
 Credence Quartet
 Credence STS6120
 Generic STIL
 as standard output
 Generic WGL
 as standard output
 IMS Vanguard
 Inovys Ocelot
 KVD M2
 LTX Fusion CX
 LTX Fusion HF
 LTX SynchroMaster
 LTX Trillium
 MOSAID MS4000
 NPTest Sapphire
 OPENSTAR T2000
 Schlumberger S9K
Overview
The purpose of    is to clean or condition VCD/EVCD files. The user can use the    for any manipulation on the source VCD/EVCD file.
Both input and output for
   are VCD/EVCD files.
This process would typically include such functions as:
1. Align Edges to Grid
2. Transition masking
3. Signal Masking
4. Mask Differences
5. Cut Vcd
6. Shift Vcd
7. Change Value(s)
8. Virtual signals generation
9. Find Clock
10. Remove Spikes
11. Expand Buses
12. All operations could be executed on a conditional basis
Event driven to Tester Simulation results -
WGL/STIL ATPG to Tester -
Verification of test program before silicon -
Simulate a test program -
Simulation Data processing -
VCD/EVCD files to tester files -
 new
Directly extract timing into WaveWizard Constructs -
Suite of tools enables users to expand use of STIL - new