Introduction
 Capabilities and
   Operation


 Supports the following
 system platforms:
 Sun Solaris
    (2.6 and higher)
 Windows NT
    2000 Pro
    XP Pro
 Linux
    (kernel 2.4 and higher)



 Verigy V83000
 Verigy V83000f660
 Verigy V93000
 Verigy V93000 Pin Scale
 Teradyne Catalyst
 Teradyne Flex
 Teradyne J750
 Teradyne J971
 Teradyne J973
 Teradyne UltraFLEX
 Advantest T2000
 Advantest T66XX
 Credence Kalos
 Credence Quartet
 Credence STS6120
 Generic STIL
 as standard output
 Generic WGL
 as standard output
 IMS Vanguard
 Inovys Ocelot
 KVD M2
 LTX Fusion CX
 LTX Fusion HF
 LTX SynchroMaster
 LTX Trillium
 MOSAID MS4000
 NPTest Sapphire
 OPENSTAR T2000
 Schlumberger S9K

Scan Converter - product overview
  • WGL conversion
  • STIL conversion
 Is a low cost option for converting scan tests, Serial or Parallel, into tester formatted patterns and timing. The tool accepts either WGL or STIL formats which are the most widespread vector formats produced by today's leading ATPG tools, such as Mentor Graphics' FastScan, Synopsys' TetraMAX and similar.
 creates all files needed to load and run different testers, such as Verigy, Teradyne and LTX.
Introduction
Serial format is a format in which at every tester cycle all device signals are driven or compared, and the state is defined. Serial vectors are lines of logical states, while each line specifies the state of all signals.

Parallel format is a description of the internal scan chains in the device and the state of each cell. Since in production test, the device is accessible only through its external pins, that description is not directly applicable for the tester and the tool has to "serialize" it (take the internal states description and serially drive it through the device pin).

The scan data in both formats, WGL and STIL, consists of 3 sections: Signals, Timing and vectors.    converts all 3 to the target tester formats:

The Signals section lists the device signals and their direction.

The Timing section describes the timing for the vectors. Each signal is assigned with specific timing for data drive changes or compares device data to test vector data.

The Vectors section describes the state to be driven to each device pin or logical state, to be compared to the device pin state on a tester cycle basis.
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Capabilities and Operation
  • Convert scan tests, (Serial or Parallel), written in either WGL or STIL syntax from ATPG sources, into tester formatted patterns and timing.
  • Generate patterns for many different testers, in which the user has a choice of the output format.
  • Translate Parallel scan vectors into Serial tester vectors.
  • Take a Parallel scan vector and write a tester Parallel vector.
  • Allow incremental operation (useful when multiple patterns share same timing).
  • Allow high level of customization.
  • Allow the user to have control of the output pattern format.
  • Allow signals manipulations such as grouping/reorder etc.
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The wizard platform click to enlarge
Event driven to Tester Simulation results -
WGL/STIL ATPG to Tester -
Verification of test program before silicon -
Simulate a test program -
Simulation Data processing -
VCD/EVCD files to tester files -
 new
Directly extract timing into WaveWizard Constructs -
Suite of tools enables users to expand use of STIL - new