Verigy adds test generation software to SOC tester Test Industry News, October 30, 2001: Verigy Technologies has released the SmarTest Program Generator (SmarTest PG) software for its 93000 system-on-chip (SOC) testers. The company claims the combined products will help accelerate product development and reduce the cost of test. SmarTest PG incorporates technology provided by Test Insight-- an Verigy partner in the delivery of design-for-test (DFT) productivity tools. By incorporating Test Insight software that supports multiple clock domains, SmarTest PG provides access to concurrent test capability within the Verigy V93000. SmarTest PG replaces the scripts and tools that are typically used to translate EDA output to a tester-ready test program, and it enables the 93000 to directly accept EDA-generated design and simulation files. SmarTest PG generates loadable Verigy V93000 program files, with output features including pattern generation, timing and AC specifications, pin configurations, and DC levels. The product offers graphical timing capture, simulation and output analysis, I/O support, equation-based timing, and incremental program generation. Device cycle timing is captured and incorporated into a test that exercises the full range of device behavior. The software's flexible graphical editor lets you manipulate and analyze simulation waveforms in real-time throughout the conversion. Tester-ready output can be loaded onto the Verigy V93000 for serial or concurrent testing. The analytical tools in SmarTest PG help you understand complex design scenarios, so you can use the device timing specifications from the EDA environment within the test environment. In addition, you can begin test development earlier in the design process to produce high-quality pattern generation, while reducing the downstream test debug and shortening time to volume. Back to press release list