Supports the following  system platforms:  Sun Solaris     (2.6 and higher)  Windows NT     2000 Pro     XP Pro  Linux     (kernel 2.4 and higher)  Verigy V83000  Verigy V83000f660  Verigy V93000  Verigy V93000 Pin Scale  Teradyne Catalyst  Teradyne Flex  Teradyne J750  Teradyne J971  Teradyne J973  Teradyne UltraFLEX  Advantest T2000  Advantest T66XX  Credence Kalos  Credence Quartet  Credence STS6120  Generic STIL  as standard output  Generic WGL  as standard output  IMS Vanguard  Inovys Ocelot  KVD M2  LTX Fusion CX  LTX Fusion HF  LTX SynchroMaster  LTX Trillium  MOSAID MS4000  NPTest Sapphire  OPENSTAR T2000  Schlumberger S9K	Overview HDL-Link  - like Virtual Test Wizard - is a test program simulation and debug environment.  HDL-Link  is designed to create a Verilog testbench from Wave Wizard project. The Verilog testbench: Instantiates the device model Drives the inputs Compares output coming from the device signals in a methodology that is emulating the tester behavior This allows the design and test teams to exercise the tests, as it will be used on the tester before silicon exists. In the normal flow, a failure in a test program executed on the tester could be failing for main three reasons: The test patterns were created in a wrong way, e.g. forcing an internal node which could not be done with the actual silicon. The conversion from the design environment into the tester syntax was wrong, e.g. a missing signal in the files. The silicon and the device simulation model do not match. The wizard platform click to enlarge It is only the last reason that is of real interest when silicon arrives. The first two could be resolved using  HDL-Link  as the test will run in the same way as it will eventually run on the tester.	Event driven to Tester Simulation results - WGL/STIL ATPG to Tester - Verification of test program before silicon - Simulate a test program - Simulation Data processing - VCD/EVCD files to tester files -  new Directly extract timing into WaveWizard Constructs - Suite of tools enables users to expand use of STIL - new